Static storage devices such as SRAM cells use a write operation to store data in the cell and a read operation to sense the data stored in the cell. To ensure no read data disturbs occur, the write operation needs to write full power supply voltage levels to the SRAM cell so when the data is read it is not corrupted. In current SRAM cell designs, large P-channel field effect transistors (PFETs) are required to supply retention and write-recovery currents to maintain the full power supply voltage level. As integrated circuits become smaller and denser and as power consumption specifications for battery powered integrated circuits decrease, along with power supply voltages, the present SRAM cell designs are increasingly inefficient in both silicon area used and power consumed.
Therefore, there is a need for writing full power supply voltage levels to SRAM cells that have reduced area requirements and low power consumption.